GSoC/GCI Archive
Google Summer of Code 2013


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coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most of today's computers. coreboot performs the required hardware initialization and then executes a payload to extend features

Some of the many possible payloads are: a Linux kernel, FILO, GRUB2, OpenBIOS, Open Firmware, SmartFirmware, UEFI, Etherboot, SeaBIOS (for booting Windows XP, Windows Vista, Windows 7, NetBSD and Linux), ADLO (for booting Windows 2000 and OpenBSD), Plan 9, or memtest86.

As well as the payloads, coreboot relies on critical systems tools like flashrom. Flashrom is a utility for identifying, reading, writing, verifying and erasing flash chips. It is designed to flash binary ROM images on mainboards, network/graphics/storage controller cards, and various programmer devices.

The initial motivation for the coreboot project was for the maintenance of large clusters, but unsurprisingly, interest and contributions have come from people with varying backgrounds.

The latest version of coreboot can be used in a wide variety of scenarios including clusters, embedded systems, desktop PCs, laptops, and servers with the latest x86 silicon from AMD and Intel. The latest development in coreboot is that it is used by Google ChromeBooks.


  • A universal USB-based FWH/LPC/SPI programmer While flashing SPI chips can be done externally with relative ease using flashrom, hardware to program FWH and LPC chips is beyond the reach of most enthusiasts. Cortex-M processors have become well-established in the open source community due to their low cost and extensive ecosystem. This makes them an ideal candidate for a universal ROM programmer. I propose a hardware/software/firmware ecosystem for a universal ROM programmer based on Cortex-M processors.
  • flashrom: infrastructure improvements galore The plan is to tackle some long-standing infrastructure problems that have to be fixed eventually if we want to continue current and future flash chips. The expected outcome of my GSoC programming are the following new features: - Support for multiple read/write operations - Support for 4-byte addresses - Improved (SPI) probing
  • Prepare for the lack of super-io UARTs and serialports on new mainboards There are some common debugging problems people come across when starting a port of a new mainboard for coreboot. First is the flashchip being soldered on the mainboard and second is the lack of serial port connector. I attempt to attack both of these on some level. My primary goals are to add support for memory-mapped serial UARTs and the ECHI debug port mechanism on the commonly used payloads, and to integrate a pre-OS flash writing mechanism in the toolchain to allow easy and safe deployment of new coreboot builds.
  • Test set-up for the coreboot distributed firmware test environment featuring greater extensibility, enhanced automation, concurrent high speed firmware flashing and decentralized operation. The proposed system provides convenient and inexpensive architecture for interfacing the coreboot test server to systems under test (SUT). Each SUT has a Controller board for controlling and monitoring the SUTs and an In Circuit Programmer based on FT232H USB 2.0-Serial Bridge. A cluster of these SUTs connect to a concentrator computer based on Raspberry Pi (RasPi) board where it provides functions of flashing, controlling and monitoring of the SUTs. A large number of such clusters may exist which could be connected to a common LAN or the internet so that these concentrators can be accessed remotely from any computer via SSH and an individual SUT may then be controlled through the software within the concentrator. Programmable USB Power-strips are provided such that individual switches can be programmed by the test server to control power to the SUTs and other peripherals.